Name: Reduce SMT Parasitic Design Failures with Innovative Filter Topologies
Uploaded: 2025-09-16T19:31:40.385Z
Duration: 51 min 16 s
Description: Reduce SMT Parasitic Design Failures with Innovative Filter Topologies

Transcript for "Reduce SMT Parasitic Design Failures with Innovative Filter Topologies": Welcome, everyone, to today's webinar, reduce S and T parasitic design failures with innovative filter topologies. We will begin in a few minutes. Sure. I can share. Okay. Hello, everyone. Welcome. My name is David Vai. I am the product marketing, management director. And on behalf of Cadence, I'd like to welcome you to today's webinar, reduce SMT parasitic design failures with innovative filter topologies. Before I introduce today's presenters, I'd like to go over a few housekeeping items. All attending lines are muted to prevent background noise. There will be a question and answer session, segment at the conclusion of today's webinar. If you do have any questions during the presentation, navigate to the engagement panel on the, right side of the screen, locate the q and a tab, and type your question into the text box provided. We will attempt to answer all the questions at the end of the webinar. However, if we do run out of time, the questions may be answered via email within the next few days. Please ask your questions early so that we can get them queued up and ready to go for the q and a session. Today's webinar is being recorded, and a link, to the recording will be emailed you, in the coming days. And before I, introduce today's speaker, I'd like to give you a little information on the latest RF design technology from Cadence. At this, year's past IMS in San Francisco, we introduced Virtuoso Studio RF. This new platform is built on top of the microwave office framework and provides a highly interactive layout forward design cockpit for silicon based RF system development. We're leveraging a lot of, proven and trusted cadence technology, from this platform. One can develop silicon mimic and small scale RFIC designs, using Virtuoso enabled PDKs, simulated with Spectre circuit simulation and the proven e m x planar three d, InDesign analysis. And and then designs generated in Virtuoso Studio RF can be consumed in the larger Virtuoso heterogeneous integration flow. We're looking to be able to really provide a solution for, front end module design, with multiple technologies. Some of the envisioned flows that we support with this new platform are advanced RF analysis, at circuit and system levels, analysis such as, load poll analysis or nonlinear stability analysis as well as system analysis. As I mentioned, the silicon mimic and small scale RFIC design and, module design. So this is a new product. You could find out more on the Cadence website. It's Virtuoso Studio RF. Now at this point, let's, introduce our speakers. Our main speaker today is Dan Swanson. Dan has served for many years on the editor editorial board of the IEEE Transactions on Microwave Theory and Techniques and the IEEE Microwave and Wireless Components Letters. He has published numerous technical papers and has presented many workshops and short courses and holds two patterns. He is teaching courses on EM simulation and filter design in The US and Europe and is the principal author of Microwave Circuit Modeling Using Electromagnetic Field Simulation published by Artech House. Dan, founded DTS Associates in 2015 after more than four decades as a design engineer with expertise in high q filters and multiplexers for communication applications, EW systems, and PCB filters. So he is a great candidate for talking about, today's subject. Joining him, we will first hear from Chris DiMartino, an applications engineer at Modelytics. Prior to working at Modelytics, he spent time at several other companies developing and testing our microwave components and assemblies for various applications. In addition, Chris spent several years working as a technical editor for an industry publication. He has a BS in electrical engineering from State University of New York at Binghamton and an MS in electrical engineering from Polytechnic University. So at this point, I'm gonna hand it over to Chris. Hello, everyone. So we just like to kick things off today by talking a little bit about the Monolithic's complete library. You're gonna see some of these models in action later on, but let's talk about this library. The latest library is version 24.7 for the Cadence AWR design environment, and this library includes over 28,000 components from over 75 vendors. This, the Monolithic's complete library includes Monolithic's large collection of microwave global models for capacitors, inductors, and resistors. And like I said, you're gonna see more of that later on in this presentation. So let's talk a little bit more about these microwave global models. These are very powerful models that are highly scalable. These models are developed by actual measurements that are performed in the model ethics lab. These models scale with respect to part values. So with that being the case, that makes these models very ideal for tuning and optimization. And also note that a single model typically covers the full range of part values for a a given vendor part series. In addition to that, these models scale with respect to substrates and solder pad dimensions. And, also, the solder pads can be de embedded from the model, and that makes these models very useful for EM circuit cosimulations. So you can de embed the pads from the model, and then you can simulate the solder pads in the EM simulator. So the models give you that flexibility for EM circuit cosimulations. So on the right, you see an example of a band pass filter that was designed with AWR design environment and the Monolithic's microwave global models. And on the bottom, you see the results. You see the simulated results and the measured data. And for more information, you can see ModelLytics application of 66. And with that, I'll turn it over to Dan. Thanks, Chris. Welcome everybody. You've seen the title. We're gonna talk about lumped element filter design in the SMT environment world, the PCV world. And any lumped filter prototype that you look at is, of course, monotonic in the stop band. There's no spurs, there's no parasitics to take into account, but a, SMT filter is gonna have spurs in the stop band. And it turns out that the topology you choose, can greatly impact the spurious performance. And the surprising thing, to me and probably to you is that SMT caps actually have a lower series resonant frequency than SMT inductors. Another key point is that, when you translate that lumped element prototype into the SMT world, the element values can shift by quite a bit. And then finally, we're gonna talk about optimization and basically, standard part value optimization from my point of view just really doesn't work. Only a few part types that you can access offers small steps in value. And even then, not all of those values might be in stock at Digi Key or Mouser or whoever your vendor is. So the key concept here is to optimize the layout around stock standard part values, and you'll see that in the examples. So one of the most basic topologies that you'll find in just about every textbook is this, top coupled prototype. You have shunt resonators coupled by capacitors and coupling capacitors at the input and the output. And if you look at the frequency response of that lumped element prototype, of course, there's no spurs in the stop band and the coupling elements are all high pass type elements. They're series c's. So you get a sharper rejection on the low side of the filter than you do on the high side of the filter. And we can translate that into the PC board environment using the model ethics library. One thing I should mention is the default pad size on the inductors had the width of the pads is 26 mils and on the capacitors, the default is 22 mils on the width. I compromised and and set those to 24 mils to reduce, the amount of discontinuities that we might have to to model. So I wanted to keep the schematic as simple as possible. So we're looking at Rogers 4,350 for the substrate. We've got an Epsilon r of 3.66, 10 mil thick. We're using, Kia Serra four zero two AccuP caps and CoilCraft four zero two DC inductors. This inductor series has, tenth of a nanohenry steps up to about, I think it's, 10 nanohenries, so pretty fine steps. And initially, we'll allow continuous tuning on the, the SMT parts, And then later, we'll fix those values and adjust the layout. There is a we do need a VIA model and there's a built in Via model in microwave office. But I kinda wanted I wanted to double check the model to make sure it was gonna be accurate enough for our work. So I did an FEM simulation of the Via and de embedded it down to the edge of the pad and then compared that to the, analytical model. And they're they're actually the analytical model in this case is actually quite good. The black trace with the diamonds is the FEM. This, purplish trace with the squares is the, analytical model. And if we fudge that analytical model by telling it, well, the the substrate height is really 7.7 mils and not 10 mils, those two curves lie on top of each other. So that's what we're gonna do for the, via modeling. I could monkey with the diameter of the via, but I don't wanna do that because I don't want uncertainty in my, layout geometry. I wanna be able to take a DXF of the layout and translate it into into my fab tool. And so here's what, that layout, looks like in microwave office. Oh, this is this is interesting. The the the parts are underneath the metal instead of on top of the metal in this view. But, yeah, we can we can get to this, layout directly from our our schematic. And when you, simulate it, we get this very nasty spurious response, pretty close into the passband. We're we're centered at one gig. It's a 20% bandwidth filter at one gig, and we've got pretty serious spurs starting, just be just below four gigahertz. But there's a couple of interesting tricks you can do. In the model ethics models, there's various simulation modes. Sim mode zero includes all the parasitics. So this this is assuming all the parasitics are active, for all the components. We can do some exploring using that SIM mode. If we take our our, circuit and set the inductors to SIM mode one, that makes the inductors ideal. So we've got ideal inductors and the full parasitics on the caps and the spur is still there. And then we can do the opposite. We can set SIM mode equal one on the capacitors, make them ideal. And now we've got the full parasitics on the inductors and the spur goes away. So there's a a real strong hint there that the problem is the capacitors. And when you look into it deeper, you discover that a 3.7 puff cap SMT cap has an series resonant frequency of about 4.1 gigs, which is exactly what we're seeing here. And the series resonant frequency on a three nanohenry inductor is way out at 15.8 gigahertz. So it's not the problem. The the capacitors are the problem. If you look at the construction of of the capacitors, the conventional construction is on the left. You've got interleaved fingers in a dielectric layer, But there's this other version of the capacitors called the AccuP series, and it's actually a thin film capacitor, only two plates, and it's buried then in an SMT type package. So you would think the series resonant frequency behavior might be different between these two because the way they're constructed is is so very different. But it turns out there's very little difference. If you look closely at the Kyocera data sheets for the multilayer cap, for a capacitance of four picofarad, it says, yeah, you're gonna you're gonna get an SRF right around four gigahertz or a little bit higher. And if you do the same thing for the AccuP caps, they actually put the SRF right here in the data sheet. And again, for 3.7 puff, it says, yeah, you're gonna get an SRF around 4.1. And that was really surprising to me at first because I'm used to working in a thin film environment, you know, thin film on ceramic or in an MMIC environment with gallium arsenide. And in those environments, we assume that the SRF, for a capacitor is gonna be much higher than for an inductor. A printed inductor SRF can fall very rapidly as you add turns. But in the SMT world, the SRF for the inductor starts high and it does fall as you add turns and the inductor value increases. But the SRF for the capacitor starts out low and it stays low. And again, we might assume that the ACCUPE and the multilayer cap SRF could be radically different, but that doesn't appear to be the case. I did some experiments with smaller case sizes and that does make a difference, but it's not a huge difference. And it's and the SRF is, for the capacitor is not that sensitive to, value. And you could see that from the the previous curves. So now we want to, fix the values of the SMT parts so that we can order them and and build a filter. And to do the optimization now, we're gonna choose the closest values on the standard values for the SMT parts and we're going to insert transmission line lengths to use for optimization. So we're optimizing on the layout rather than on the part values. And in this case, all I needed to do was add lengths on the shunt legs and I could get the optimization to converge at the ideal response. And so here's the the final layout. We've got three nanohenry inductors in shunt. We've got 3.7 puff capacitors in shunt. And to fine tune the response, we've added a four mil length of transmission line here and a five mil length transmission line on the center, resonator. And oh. Oh. Alright. This is this is the measured data, guys, the measured data didn't get in here. This is not the latest update. Anyway, yeah. I I apologize. I've I've got measured data that that should have showed up here. But, anyway, with that standard configuration, you get this close in spur. So how do we get away from that? Well and the other point is that, yes, the values in the SMT world do change, but they're not radically different than the lumped element prototype. But these differences will be bigger in some of the other examples, that we're looking at. So what if we go to a different, topology? What if we use, inductors to couple in rather than capacitors? And that prototype again looks looks nice in the, in the lumped prototype world. Now all the coupling elements are low pass type elements and so you get sharper rejection on the high side than you do on the low side. And because of the way the pads are laid out on the inductors, there's not a lot of room off the, end of the inductor pads. So I'm gonna just preload some, five mil lengths of line around the inductors just to make a little more space in the layout. And you can optimize on that, and this is the first solution. The the shunt capacitors wanted to be eight point one and nine point three. Those are standard values except they weren't currently available at Digi Key or Mauser. So I had to choose different values for the capacitors. But this is what it looks like with, the continuous tuning. The stop band is quite nice. We don't have that close in spur like we had with the other topology. And so now we wanna finalize it. And again, this was the second attempt because I the original shunt c values weren't in stock, so I had to change those and which changed the layout. And again, I've inserted transmission line lengths in order to, tune the layout. And so this is what that looks like. Now the shunt caps are seven point five and eight point two. And here I've added 6.5 mils of transmission line. And on this center one, we've added quite a bit of transmission line. And the, originally, the shunt inductor was three nanohenries, and it ended up being 3.4 nanohenries in this case. And, again, we're missing the, measured data, which is really unfortunate, but maybe we can correct it in a handout that we can send you or something. Hey, Dan. Maybe during q and a, we can locate the the correct slides. Well, I could yeah. I could bring up my copy here and I and show those real quick. Yeah. I I I'm I'm I'm texting with, with Cal offline, and we'll see what we can do. But Okay. Alright. Thank you, David. Yeah. Because the the agreement is really quite good. It's it's you really need to see it. And in this case, the final SMT values are actually quite different than, the original prototype values. So when you're looking at lumped element prototypes and you say, oh, this inductor looks it's kinda big or this capacitor looks kinda small, you kinda need to do your first SMT prototype to see where those are actually gonna end up because of the the parasitics of the SMT parts, do modify things. So in traditional lumped element filter design, the goal was often to minimize the number of inductors because back in the day, an inductor was assumed to be an air coil or maybe a toroidal coil at lower frequencies. But in this SMT technology, the inductors and the capacitors are equally easy to place. There's no big no big difference as far as that goes. So considering the very low SRF of the SMT cap, it probably makes sense to search for minimum capacitor topologies. And it always makes sense to minimize the total element count, which leads us to the next topology, which is the Coward Chebyshev, elliptic. And this is a a well known topology. You can synthesize it. You can find analytical equations, to give you element values. You can do higher order filters. I stuck with the n equal three here just to make it similar to the other filters. And also, you know, in a lot of cases where you're using an SMT filter, you don't necessarily need a really high order filter, but you need a really small filter or a filter that's very compatible with the PC board environment. But if we, here's our first example where the inductors I've I've, you know, lumped element prototype, if we change the order of these elements, if we put the inductor on the outside and the capacitor to the inside, it shouldn't make a difference. Well, it doesn't make a difference. But of course, in the SMT world here, it potentially does make a difference. So in this first example, I put all the inductors towards the middle. And now we're working on a 20 mil thick, taconic TLX board. This was didn't wanna work very well on the 10 mil thick board, so I went to the 20 mil thick TLX board. And now the via modeling has changed with the extra thickness. Now the delta between the standard analytic model and the FEM model is a lot bigger. But what I did is I went ahead and gave the vias their own substrate definition and I changed the thickness again of the substrate. And if you do that, you get the the analytic model to line up exactly with the FEM model. And again, this is actually the second attempt for this design. I thought I was done and I went to order parts and there was a couple of parts that I couldn't get. So I had to go back and modify the element values to, ones that I could actually get quickly off the shelf. And here's what that layout looks like. The 50 ohm line is quite a bit fatter on this thicker substrate, but I've stuck with the 24 mil pad geometries here. And again, with the the tuning, in this case, I really only had to tune the shunt arms with the extra line lengths and, in this arm it was 12 mils and in this arm it was eight mils. And again, I've added some extra buffering here around the inductors just to make some more room around the, the center. And the t model is a x model in Cadence. It it's based on EM simulation. And, with this topology, we get a a pretty nice response in the SMT world. And because we've got transmission zeroes, the the bandwidth here at 30 dB down is a lot narrower than the other prototypes because we've got the close in transmission zeroes. But we're maintaining spurious response below 30 dB out to 10 gigahertz. So what if we flip the order? What if we put the capacitors toward the middle and the inductors toward the outside? And, of course, there's couple more variations you could do, but that's kind of an obvious one maybe to try. And you can get it to converge, the the optimization to converge. And again, we're tuning with the transmission line lengths. And now our our ugly spur close in is back. And it it just has to do with the position of the capacitors in the in the topology. So if we summarize here, this these are the prototype values for the this powered Chevy Chef, prototype. And if you look at rev a, which is the one that works nicely, the capacitors in general are a little bit bigger than the prototype, which in in general is good. You you don't wanna try to realize a really small cap if you can help it. And the inductors are smaller than the prototype, which is also good. You know, the smaller you can make the inductors, the lower the higher the SRF of the inductors and the better chance that you're gonna get a, a good stop band response. And the rev b that has the spur is kinda just the opposite. You know, the inductors tend to be the same or or as the prototype and the induct the capacitors tend to be smaller. So, you know, which would you rather have, a 2.5 or a 1.6? Well, you'd rather have the the bigger one. And the same here with this really small one, even though that delta is all that not not that great. But in this case, the, you can you can see a pretty strong difference in the final element values between the two versions. So in conclusion, obviously, the lump filter prototype is monotonic and the SMT filter has spurs. This SMT filter topology has a big impact on the spurious performance. And kind of the surprise in all this, for me and maybe for some of you is that the series resonant frequency of those caps is actually much lower than for the inductors. And the PC board thickness and epsilon r do come into play. Of course, you know, your major parasitic is probably the shunt c of the pads, that that the parts are mounted on. So we probably wanna consider minimum capacitor topologies when we can. Also note that the element values for the SMT filters can be radically different than the lump prototype values. And, you wanna optimize on the layout around stocked standard part values. David, I've got a few extras. Oh, oh, oh, see, Phil's Phil's pictures didn't get in here either. What should we do? Well, first, I come off mute. And, was that your last slide? Because I I That's that's my last slide. Yeah. You sure? Because we're seeing more slides in your deck. Really? I don't know why. Yeah. That will yeah. So somehow your conclusion slide moved forward. I I don't know. No. Then this this was designed to be in extras, If I had time, I could go ahead and do these, but they were designed to be extras. Well, you you have time if you wanna take it and, Okay. Okay. We've got some questions. So so you've got time. Why don't you do your extra? And then what we'll try to do is, Dan, the the deck you sent to us, we've looked at. We don't we're not seeing the measured data in those plots. So if you have that, what we're thinking is, why don't you go through your extras and then you can share your slide. We'll try that and and we'll and then we'll go to the q and a. Okay. Okay? Alright. Well, one other topology that you might look at is the so so called minimum capacitor topology. And again, this one is known, in the literature. Unlike the cower, you just have a single shunt branch. You don't have the two, resonant shunt branches. But it does work. But the shunt inductor controls the bandwidth of the filter. And at 20% bandwidth, that inductor is is small. It's only 1.2 nanohenries. At 1.2 nanohenries, I would consider printing that inductor rather than, trying to make it an SMT part. And because we have so few element values, the optimization got a little bit tricky with this design too. So because of this bandwidth, issue, this one might actually be more useful for bandwidths that are a little bit broader. But, fundamentally oh, and there's the layout. But, fundamentally, it has a nice stop band. So it's it's a candidate, for future for future work. Okay. How do I get to my slide deck? Oh, wait. You have to you still have more, Dan. And if you wanted to show Oh, yeah. Okay. So these made it in. Okay. So the major data that you haven't seen was produced by Phil Jobson in Santa Rosa, California. He's a consultant and a good friend of mine, and he has, his own LPKF laser machine, and he's got the old older version that's the mechanical drilling and routing. So he made the PC boards. He has a process for doing the vias, and, he put down solder paste and hand placed the components and did the reflow with a, hot stage. And one more. So here's his test set up. He's got some pretty sophisticated, fixturing that he's developed for himself and, so he could accurately do the, the de embedding. So a big shout out, a big thank you to Phil for his work on getting getting us the test data. Okay. Thanks. And do you mind if you okay. There we go. So we got a number of questions. Dan, why don't you try and and, Kale, you can help me with this. The on the left side of the screen, Dan, your screen, does does he hit screen to to do screen. Yeah. Okay. And then and then bring up your slide deck with with the measured data that you wanted to show off? Yeah. You have some choices there. Chrome tab, window, entire screen. Yeah. Hit entire screen. I did. Choice. Yeah. Okay. K. Oh, okay. So Now you have to bring up the deck? Yeah. So close so close that. Let's try again. Close the top here? Well, stop stop sharing that. Stop sharing your screen. Yeah. And then hit share screen again, and then we'll get another choice there. We'll try a window or we'll try Chrome tab until we get the right one. I'll I'll I'll try entire screen. Okay. That doesn't seem to be working. Showing your your yeah. It's it's sharing the desktop. You need I think you need to bring up the A window? Okay. I'll let I'll let you let's try a window. While we're waiting for Dan, this is a good time for me to say that at the end of the q and a, we will launch a survey, and we encourage, our attendees to fill out the survey. It helps us to, you know, get your feedback and and apply that to future webinars. Alright. Yeah. Be able to Yeah. Okay. Resolve it. So we'll just move to the q and a. Yeah. Let's let's do that and and we'll, update here. Yeah. I appreciate that, you you sound like you had excellent, correlation between measured and simulated data, Dan. Yes. Yeah. Very nice. And, there was actually a question with regards to the slide deck. I think, Kaylee, you answered that. Are are we making the the slides available or just the, Yeah. A recording of this of this webinar will be made available. Link will be sent to everyone that attended to, to show this entire webinar. The slides themselves won't be available. If you wanted to get some slides or some more detailed information, just reach out to your account team, and, and we should they should be able to share those one offs with you. Yeah. Sounds sounds great. Dan, related to your, I heard you talking about your your your last your extra example. And you said, like, I I think it was a small value component that you could have probably, taken care of with a gap. And here's a question related to that. Can we make the gap can we make the cap in the board or use trace cap gaps to make edge caps? Say that again. Yeah. I I understand the question. Actually, the the part I wanted to print was the inductor, not the capacitor. Okay. So so when I get a a an inductor in one of my designs that's below roughly one and a half or two nanohenries, I think again and about printing it on the PC board rather than making it an SMT part just for tolerance reasons. And at at some point, the SMTs, you run out of potential parts below about a nanohenry. Okay. And and thoughts on a trace gap to make an edge cap? You're gonna have a hard time getting enough capacitance. And I've tried interdigital, capacitors many times or several times in my career. The problem with the printed interdigital cap is as you increase the length of the fingers or the number of fingers, the shunts c parasitic, goes up more rapidly than the series capacitance. And so at some point, it's it's not very useful. So I've I've had very bad luck using printed interdigital caps in the past. Okay. Yeah. The problem is that where are the parasitics controllable enough? I think that was the last part of that. Well Oh. Yeah. Thanks, John. You you you really don't have control, you know. If you're if you're adding finger finger metal to get more series cap, you're you're adding shunt capacitance at the same time. And the shunt capacitance actually goes up faster than the series capacitance that you gain. So Okay. Okay. Sounds good. Next question is how, a transmission zero affects s parameters and how to correlate the change in s parameter plot and pole zero? Well, in the in the, is our slide deck still live here? Yeah. Yes. Okay. So in the power Chevy Chef, so the, one of the zeros is coming from this arm and the other zero is coming from this arm, and they're independent of each other. They interact, but they're fundamentally independent of each other. So you you fix one of the values, either the inductor or the capacitor, and you optimize on the other one to put the zero where you want it. So you can you can move those zeros around. And then and then finally, you wanna get to the point where you lock down both the, inductor and the capacitor. So if I go back yeah. So so literally, you can you can see these zeros move as you're modifying those element values, and you can get them I'm I'm basically looking for I picked a goal of having 30 dB down lobes here. So I was looking to get these lobes at 30 dB or below. Okay. Let's see. Our next question asked, how to conceptualize poll zero in the domain of s parameter? I don't think in terms of poll zeros. K. Yeah. I'm I'm sorry. I I I can't help you with that. Yeah. Again, you can you can synthesize this topology directly. And if and there's a textbook that actually has analytical equations to compute this topology also. But, I basically go into the synthesis program and and and synthesize this directly. But I'm not thinking in terms of of poles and zeros. Okay. Hey, Chris. Do you have anything to add from a model ethics perspective on on the device modeling and and and feedback based on what you saw from Dan? Is Chris still out there? Hello? Yeah. I'm still here. Yeah. Okay. Hi. Hi, Chris. Yeah. So no. Yeah. So this is a good example of the, you know, effectiveness of the model ethics models. I mean, if you saw the, measured data, you would have seen the very good agreement between the simulation and the measurement. So we always like to emphasize how, you know, they can help designers achieve first pass success, and the models are scalable with respect to, like we mentioned before, of substrates and and path dimensions so you can, you know, use the models according to your design requirements, and then they'll scale appropriately. So what Dan showed us, you know, some good examples of how these models can be very effective for filter designs as well as other types of designs. What you say and this is a question for both of you. The the impact of the the quality, the frequency response of the the surface mount components for for filter performance. You you you focus more on filter design and and the and and topology or are are high high, you know, expensive, high quality components worth worth the extra expense for filter performance? What what are your thoughts on that? I have a I have ideas on that. If when you synthesize one of these lumped element prototypes, if you want a perfect response, you need your element values have to have precision up to two or even three decimal places. And even the best parts we have today, you know, the best inductor you can buy is 2% tolerance and the capacitors are a little bit better than that. So, you know, generally, you wanna buy the the tightest tolerance, parts you can find. And you're still gonna have to make some adjustments, maybe do a little bit of bench tuning when you get when you get the real hardware back. I did a switch filter bank, several years ago and it's reported in a paper that was published a couple of years ago in Microwave Journal. But it was a switch filter bank that went from 900 megahertz to six gigahertz. And what I saw in that work was down around one or two gigahertz, perfect turn on was was pretty typical measured versus model. As you go higher, you know, up to three, four, now you're doing maybe a little bit of bench tuning. You're modifying a few element values. And by the time you got to six gigahertz, you might have to do a design spin, or two. So, you know, definitely down in this one, two gigahertz range, it's things are are pretty great. And then it it gets tougher as as you go higher. K. Sounds easy. Well, we have a new question that just came in. You have mentioned minimum cap topology. Could you please look on this again? Does it mean that it is possible to tune l and c values to get rid of some of the caps? Yes. If if we go back to the slides well, you know, there's there's fundamentally a difference between the there's fundamentally a difference between just whether you're using top l coupling or top c coupling. So so that's that's kinda easy. The minimum c topology, the last one I showed, that one is designed to minimize the number of capacitors compared to the number of inductors. And then in the, the Kaur Chebyshev, if you compare it to these other more more conventional layouts, there's there's basically two less components. The Coward Chevy Chef only has eight parts. These have 10, I think. Two, four, six, eight, 10. Yeah. So both of these more conventional, layouts have 10 parts. The Coward Chevy Chef only eight. So, yes, it's it's possible to to find, topologies that would minimize the number of caps. K. Well, I think I think we've gone through all the questions then. Yeah. I think so. Yeah. And, apologies that we couldn't find the, the slide with the measured data. Hopefully, we can make that available somehow. But, Dan, I appreciate the, the presentation and the work. Please thank Phil Jobson for his support on the measurement and fabrication of the filters and and Chris and the whole team over at Monolithic. We partner closely with Monolithic. They provide highly accurate models for our design. Great great folks, great company. We're we're proud to to be associated with them. And with that, please stick around. We have a, we have a a survey. It should only take a a minute or so, relatively straightforward. And on behalf of Cadence, I'd like to thank everyone for joining us today. And I'd I'd like to thank Cadence and Monolithic for their support, over the years, for this work. It's it's been a really great partnership. Thanks, Dan. Yep. I've launched the, the survey, so you should all have it, on your screen or however you see it. And then, take just a it's only four questions, so it should take you no time at all. But we really appreciate you attending. And And I think at that, we can close this close the webinar. Thank you, everyone.